Time to Digital Converter

An Introduction to Time to Digital Converter

The High end general objective TDC (HPTDC) is dependent on a number of TDC’s developed within the Micro consumer electronics group from CERN. Previous variations of common purpose TDC’s show that the idea of a pré-réglable TDC is actually highly appreciated within the high power physics neighborhood. The higher flexibility offers enabled using this type of TDC’s in several different tests with different system needs. The big programmability can also be extremely useful inside the individual experiments since the operation from the TDC could be optimized towards the actual operating conditions from the experiment that are to some extent unknown prior to the experiment is actually “turned on”.

The overall architecture developed for those previous variations of TDC’s is actually reused within the new TDC execution. This structure has confirmed itself to become extremely versatile and work nicely in many kinds of tests. The utilization of information driven structures enables the actual TDC to operate well within both brought on and un-triggered programs. A bring about matching function depending on time labels allows the actual trigger latency to become programmable on the large powerful range as well as ensures the ability of helping overlapping activates, where person hits might be assigned in order to multiple occasions. The utilization of a more contemporary technology may enable a substantial increase within the performance from the TDC whenever introducing small changes towards the architecture.

Using a forty MHz clock like a time reference is really a requirement for those LHC tests as this particular clock is actually directly obtainable in the front-end consumer electronics to synchronize the actual acquisition associated with detector signals towards the bunch crossings from the LHC device. In add-on it is needed to correctly determine the lot crossing number inside the LHC device cycle comprising 3564 lot crossing intervals.

Most customers of this type of new TDC require a time resolution from the order associated with 250ps RMS in order to measure drift amount of time in drift dependent tracking sensors. This degree of resolution can be acquired directly in the 40 MHz clock utilizing a Delay Secured Loop (DLL) along with 32 hold off elements, because done within previous variations of TDC’s. Additional potential customers like Time-Of-Flight sensors may although require enhanced resolution. Inside a 0.25 um CMOS technology time resolution could be improved to the amount of 30 -- 50 ps RMS utilizing a Phase Secured Loop (PLL) to create a 320 MHZ clock they are driving the DLL. Within the low quality mode, using a PLL isn't strictly needed. The encounter with prior TDC’s possess though shown how the generation (submission) of the stable (reduced jitter) forty MHZ clock towards the front-end may pose substantial problems. In this instance the utilization of a PLL within the TDC by itself can decrease jitter about the incoming time clock signal.

For more information please visit: Cronologic’s Time to Digital Converter