Time to Digital Converter
Time to Digital Converter Process and Uses
The actual dual-slope conversion may take quite a long time: a thousand approximately clock ticks within the scheme referred to above. That limitations how normally a measurement could be made (lifeless time). Resolution of just one ps having a 100 MHz (10 ns) clock takes a stretch percentage of 10, 000 as well as implies the conversion period of a hundred and fifty μs To diminish the transformation time, the interpolator circuit may be used twice inside a residual interpolator method. The quick ramp can be used initially because above to look for the time. The sluggish ramp is just at 1/100. The sluggish ramp may cross zero at some point during the actual clock time period. When the actual ramp passes across zero, the quick ramp is switched on again in order to measure the actual crossing period. Consequently, time can end up being determined to at least one part within 10, 000.
Interpolators in many cases are used having a stable program clock. The beginning event is actually asynchronous; however the stop event is really a following time clock. For comfort, imagine how the fast ramp increases exactly 1 volt throughout a 100 ns time clock period. Assume the beginning event happens at 67. 3 ns following a clock heartbeat; the quick ramp integrator is actually triggered as well as starts increasing. The asynchronous begin event can also be routed via a synchronizer which takes a minimum of two time clock pulses. Through the next time clock pulse, the actual ramp offers risen in order to. 327 Sixth is v. By the 2nd clock heartbeat, the ramp offers risen to at least one. 327 V and also the synchronizer reports the beginning event may be seen. The quick ramp is actually stopped and also the slow ramp begins. The synchronizer output may be used to capture program time from the counter. Following 1327 clocks, the sluggish ramp results to its starting place, and interpolator knows how the event happened 132. 7 ns prior to the synchronizer documented.
The vernier technique is much more involved. The technique involves the triggerable oscillator along with a coincidence signal. At the big event, the integer time clock count is actually stored and also the oscillator is actually started. The brought on oscillator includes a slightly various frequency compared to clock oscillator. With regard to sake associated with argument, say the actual triggered oscillator includes a period that's 1 ns faster compared to clock. When the event occurred 67 ns following the last time clock, then the actual triggered oscillator changeover will slip by −1 ns following each following clock heartbeat. The brought on oscillator is going to be at 66 ns following the next time clock, at 65 ns following the second time clock, and therefore forth. A chance detector actively seeks when the actual triggered oscillator and also the clock transition simultaneously, and which indicates the actual fraction time that should be added.
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